library IEEE; 
use IEEE.STD_LOGIC_1164.all; 
use IEEE.STD_LOGIC_ARITH.all; 
use IEEE.STD_LOGIC_UNSIGNED.all; 


entity ParallelToSerial is
    Port ( clk           : in  STD_LOGIC;                  
           reset         : in  STD_LOGIC;                 
           parallel_in   : inout  STD_LOGIC_VECTOR (7 downto 0);
           counter_in   : in  STD_LOGIC_VECTOR (3 downto 0);
           --serial_out    : out STD_LOGIC :='0'  );         
           serial_out    : out STD_LOGIC  );
end ParallelToSerial;


architecture Behavioral of ParallelToSerial is
    signal selected_bit : STD_LOGIC; 

begin
    parallel_in <= "10101111";
    process(counter_in, reset)
    begin
        if reset = '1' then selected_bit <= '0';
            
        else
		case counter_in is
                when "0000" =>
                    selected_bit <= parallel_in(0);
                when "0001" =>
                    selected_bit <= parallel_in(1);
                when "0010" =>
                    selected_bit <= parallel_in(2); 
                when "0011" =>
                    selected_bit <= parallel_in(3);
                when "0100" =>
                    selected_bit <= parallel_in(4); 
                when "0101" =>
                    selected_bit <= parallel_in(5); 
                when "0110" =>
                    selected_bit <= parallel_in(6);
                when "0111" =>
                    selected_bit <= parallel_in(7); 
		    
                when others =>
                    selected_bit <= '0'; 
            end case;
            
        end if;

    end process;

    serial_out <= selected_bit;


end Behavioral;
